Power Optimization for Digital Signal Processing in Reconfigurable Logic: Newsletter 2 EPSRC Grant Number EP/C512596/1

This paper presents power models for multiplication and addition components on FPGAs which can be used at a highlevel design description stage to estimate their logic and intracomponent routing power consumption. The models presented are parameterized by the word-length of the component and the word-level statistics of its input signals. A key feature of these power models is the ability to handle both zero mean and non-zero mean signals. A method for measuring intracomponent routing power consumption is presented, enabling the power models to account for both logic and routing power in components. The resulting models are equations which can be used to estimate the power consumed in an arithmetic component in a fraction of a second at the pre-placement stage of the design flow. The models have a mean relative error of 7.2% compared to bit-level power simulation of the placed-and-routed design.